By Manish Verma, Peter Marwedel
This e-book proposes novel reminiscence hierarchies and software program optimization ideas for the optimum usage of reminiscence hierarchies. It offers a variety of optimizations, steadily expanding within the complexity of study and of reminiscence hierarchies. the ultimate bankruptcy covers optimization innovations for functions such as a number of tactics present in latest embedded devices.
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Additional resources for Advanced Memory Optimization Techniques for Low Power Embedded Processors
On termination, the memory optimizer 28 3 Memory Aware Compilation and Simulation Framework generates application source files one for each non-cacheable memory in the memory hierarchy. Since the multi-processor ARM simulator does not support complex memory hierarchies, it is sufficient to generate two source files, one for the shared main memory and one for the local scratchpad memory. The generated source files are then compiled and linked by the underlying GCC tool chain to generate the final executable.
The sum of execution frequencies of taken and non-taken branch instruction is a constant for each run of application with the same input parameters. Therefore, the maximization of the sum of intra-trace edge weights results in the minimization of the sum of inter-trace edge weights which leads to the minimization of execution frequencies of unconditional jumps and taken branches. The trace generation optimization has twofold benefits. First, it enhances the locality of instruction fetches by placing frequently accessed basic blocks in adjacent memory locations.
A genetic algorithm is preferred over an Integer Linear Programming (ILP) based approach because of the non-linearity of the optimization problems for the subtasks. Interested readers are referred to  for an in-depth description of the compilation framework. The proposed memory optimizations are integrated into the backend of the compiler for M5 DSP. The generated code is compiled and linked to create an executable which is then simulated on a cycle accurate processor and memory hierarchy simulator.
Advanced Memory Optimization Techniques for Low Power Embedded Processors by Manish Verma, Peter Marwedel